1. Field of the Invention
The present invention relates to input buffers for integrated circuit devices. More particularly, the present invention relates to input buffers capable of compensating for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD).
2. Description of the Related Art
FIG. 1 shows a block diagram for a typical high density PLD such as the MACH130 manufactured by Advanced Micro Devices, Inc. As shown, the high density PLD includes four programmable array logic (PAL) blocks 101-104 interconnected by a programmable switch matrix 106. The PAL blocks 101-104 can be viewed as independent PLD devices on the chip, each similar to the popular lower density 22V10 PAL device, also available from Advanced Micro Devices, Inc. The switch matrix 106 connects the PAL blocks to each other and to all I/O pins 11-114 enabling a device, such as the MACH130, to provide six times the logic capability of the 22V10.
FIG. 2 shows greater detail for one quarter of the PLD block diagram of FIG. 1, including PAL block 101 as connected to switch matrix 106. Note that circuit components, such as switch matrix 106 carried forward from FIG. 1 are similarly labeled in FIG. 2, as will be circuit components carried forward in subsequent figures. PAL block 101 receives inputs, such as the 26 inputs shown, from the switch matrix 106 to input buffers 202. Input buffers 202 buffer the signals to AND array and logic allocator circuitry 204 which provides programmable AND and OR logic between the input buffers 202 and output logic macrocells 206.
The output logic macrocells 206 are programmable to provide registered or combinatorial outputs. The outputs of the macrocells 206 are provided to tri-state output buffers 208 and are also provided on feedback lines to the switch matrix 106.
Each tri-state output buffer 208 can be enabled for use as an output buffer, or disabled so that I/O ports 111 can provide input signals to the PLD. Enabling or disabling signals for the tri-state buffers are provided by the AND array and logic allocator circuit 204. When the tri-state output buffers 208 are enabled, outputs are provided from the output buffers 208 through I/O ports 111 as well as through feedback lines to the switch matrix 106. When the output buffers 208 are disabled, input signals from external circuitry are provided through I/O ports 111 to the switch matrix 106. The switch matrix 106 includes circuitry to distribute the signals received from the tri-state output buffers 208, I/O ports 111 and macrocells 206 back to the PAL blocks 101-104.
FIG. 3 shows a cut away view of a portion of the switch matrix 106 as connected to the input of one of the input buffers labeled 302. As shown the switch matrix 106 includes a plurality of pass gates 304 all feeding the input of the input buffer 302. In the switch matrix one pass gate will be enabled to supply a signal such as V.sub.S the input of the input buffer 302 as a signal V.sub.I.
As shown by the equivalent circuit for the circuitry of FIG. 3 in FIG. 4, the plurality of pass gates 304 supplying the input buffer 302 create a capacitance C while line resistance creates a resistance R at the input of the input buffer. Thus, an RC delay is added between the signal V.sub.S and the signal V.sub.I. Because the RC delay distorts the signal V.sub.S originally received, it is desirable to compensate for any RC delay of the switch matrix in the input buffer to provide an output signal V.sub.O representative of the signal V.sub.S originally input to the switch matrix.